Datasheet
DP8811+73 to U.2, 50cm cable x2 Test report
DP8811+73 to U.2, 100cm cable x2 Test report
2D drawing
- Internal Mini SAS HD 1x2, 4X(SFF-8673) to PCIe x8 Gen4 convert
- Built-in SFF-8673 1x2, 4X connector
- Input power 3.3V with TVS and Load Switch protection to protect ReDriver controller
- PCIe 4.0 8 lanes signals input and output with ESD protection
- Built-in ReDriver controller to extend PCIe 4.0, 16GT/s 8 lanes differential pair signals data link width, and may provides programmable linear equalization, output swing and flat gain.
- The PCIe 8 lanes can be bifurcated into two x4 link width to support different system topologies
- Built-in PCIe 100MHz clock buffer(Address: 0x6C) for SFF-8673 1x2, 4X to drive longer cable length. It may be buffered and fanned out to the SFF-8673 1x2, 4X clock pin dual port output.
- Built-in SMBus Switch(Address: 0x70) with Reset funtion for SFF-8673 1x2, 4X dual port SMBus communication
- Built- in SMBus bidirectional buffer repeater
- Built-in SMBus I/O Expander(Address: 0x20) for OOB(out of band) management to remote SFF-8673 1x2, 4X dual port Reset signals
- Built-in PERST# Bus Buffer Gate to be used over longer trace lengths and over longer cable lengths.
- Supports PCIe PERST# for OOB(out of band) management to remote SFF-8673 1x2, 4X dual port Reset
- Built-in WAKE# Bus Buffer Gate to be used over longer trace lengths and over longer cable lengths.
- Built-in CLKREQ# Bus Buffer Gate to be used over longer trace lengths and over longer cable length.
- D1 Green LED on indicates AIC ready
- LED1 Green OFF indicates PERST# Normal (Function intentionally inverted)
- LED2 Green OFF indicates WAKE# Normal (Function intentionally inverted)
- LED3 Green OFF indicates CLKREQ# Normal (Function intentionally inverted)
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