Datasheet
Test Report for GHC38-1951
Test Report for GHC38-1952
2D drawing
- Supports Server BMC management
- MCIO 38P to PCI Express x4 Gen 5 convert
- Built- in SFF-TA-1016/MCIO 38P, 30u”connector
- Built-in ReDriver to extend PCIe 5.0, 32GT/s 4 lanes differential pair signals data link width, and may provides equalization up to 24 dB at 16 GHz
- Built- in PCIe 100MHz Clock buffer to drive longer PCB trace lengths and longer cable, Address: 0x6C(7 bits)
- Built- in SMBus Switch, Address: 0x71(7 bits)
- Built- in SMBus I/O Expander, Address: 0x20(7 bits) for MCIO 38P PWRDIS control
- Supports PCIe PERST# for OOB(out of band) management to remote MCIO 38P Reset
- Built- in WAKE# bidirectional voltage-level translator for Open-Drain output to be used over longer PCB trace lengths and longer cable
- Built- in CLKREQ# bidirectional voltage-level translator for Open-Drain output to be used over longer PCB trace lengths and longer cable
- Input 3.3V with bidirectional TVS protection
- Input 3.3V provides 3A current Load switch and reverse current protection
- LED1 Green LED on indicates AIC ready
- LED2 Green LED on to off indicates PCIe WAKE# signals
- LED3 Green LED on to off indicates PCIe CLKREQ# signals
- LED4 Green LED on to off indicates PCIe PERST# signals
