Datasheet
2D drawing
- Supports Server BMC management
- Supports Industrial Grade temerature range
- The card should be compliant with PCIe 4.0 CEM spec
- Built- in EDSFF 2C with latch connector
- Built- in PCIe ReDriver to extend PCIe Gen4, 8-Lane data width link signals
- Built- in PCIe 100MHz Clock buffer to drive longer trace lengths and longer cable, Address: 0x6C(7 bits) for BMC management
- Built- in SMBus I/O Expander, Address: 0x21(7 bits) for Gen-Z 2C PWRDIS control
- Supports PCIe PERST0# for OOB(out of band) management to remote Gen-Z 2C Reset
- Supports PCIe PERST1# for OOB(out of band) management to remote Gen-Z 2C Reset
- Built- in WAKE# bidirectional voltage-level translator for Open-Drain output to be used over longer trace lengths and over longer cable - Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- Built- in CLKREQ# bidirectional voltage-level translator for Open-Drain output to be used over longer trace lengths and longer over cable - Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- Built- in PWRBRK# Bus Buffer with Open-Drain output to be used over longer trace lengths and longer over cable
- Built-in 12V Hot Plug Power with eFuse protection for Gen-Z 2C
- Programmable Current Limit: 6.5A
- Programmable Inrush Current Slew Rate
- Thermal shutdown protection and fault alert
- Back-to-Back (B2B) FET Operation
- Built-in 12V input with 400W TVS(TRANSIENT VOLTAGE SUPPRESSOR) ESD protection
- Built-in 12V output with 30-V, N channel NexFET power MOSFET, 32 m ohm
- Built-in 12V output with SCHOTTKY BARRIER Power Rectifier
